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features ? single power supply operation - 5.0 v 10% read/program/erase ? high performance read - 55/70/90 ns access time cost effective block architecture - one 16 kbytes top or bottom boot block with software lockout - two 8 kbytes parameter blocks - one 96 kbytes main block - one 128 kbytes main block automatic erase and program - typical 15 s/byte programming - typical 40 ms block or chip erase hardware data protection data# polling and toggle bit features low power consumption - typical 10 ma active read current - typical 40 ma program/erase current - typical <0.1 a cmos standby current high product endurance - guarantee 10,000 program/erase cycles - typical 50,000 program/erase cycles - minimum 10 years data retention industrial standard pin-out and packaging - 32-pin plastic dip - 32-pin plcc manufactured on 0.30 m process - fully compatible with previous 0.35 m version general description the pm29f002 is a 2 megabit, 5.0 volt-only flash memory organized as 262,144 bytes of 8 bits each. this device is designed to use a 5.0 volt power supply to perform in-system programming, 12.0 volt v pp power supply for program and erase operation is not required. the device can be programmed in standard eprom programmers as well. the 2 megabit memory array is divided into five blocks of one 16 kbytes, two 8 kbytes, one 96 kbytes, and one 128 kbytes for bios and parameters storage. the five blocks allow users to flexibly make chip erase or block erase operation flexible. the block erase feature allows a particular block to be erased and reprogrammed without affecting the data in other blocks. after the device performed chip erase or block erase operation, it can be reprogrammed on a byte-by-byte basis. the device has a standard microprocessor interface as well as jedec single-power-supply flash compatible pin-out and command set. the program operation of pm29f002 is executed by issuing the program command code into command register. the internal control logic automatically handles the programming voltage ramp-up and timing. the erase operation of pm29f002 is executed by issuing the chip erase or block erase command code into command register. the internal control logic automatically handles the erase voltage ramp-up and timing. the preprogramming on the array which has not been programmed is not required before the erase operation. the device also features data# polling and toggle bit function, the end of program or erase operation can be detected by data# polling of i/o7 or toggle bit of i/o6. the device has an optional 16 kbytes top or bottom boot block with a software lockout feature for data security. the boot block can be used to store user secure code. when the lockout feature is enabled, the boot block is permanently protected from being reprogrammed. the pm29f002 is manufactured on pmc?s 0.30 m advanced nonvolatile technology, p-flash?. the device is packaged in a 32-pin dip and plcc with access time of 55, 70 and 90 ns. pmc 2 megabit (256k x 8) 5.0 volt-only cmos flash memory programmable microelectronics corp. issue date: march, 2001 rev:1.0 advance information pm29f002 1
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 connection diagrams logic symbol 32-pin plcc 2 20 19 18 17 16 15 14 5 6 7 8 9 10 11 12 13 1 2 3 4323130 a12 a15 a16 v cc we# a17 i/o1 gnd i/o2 i/o3 i/o4 i/o5 i/o6 i/o0 a0 a1 a2 a3 a4 a5 a6 a7 29 28 27 26 25 24 23 22 21 a14 a13 a8 a9 a11 oe# a10 ce# i/o7 nc 18 8 a0-a17 i/o0-i/o7 ce# oe# we# 32-pin pdip 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 i/o0 i/o1 a1 a0 i/o2 gnd v cc we# a17 a14 a13 a8 a9 oe# a10 a11 ce# i/o7 i/o6 i/o5 i/o4 i/o3
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 product ordering information 3 pm29f002 t -55 p c temperature range c = commercial (0 c to +70 c) package type p = 32-pin plastic dip (32p) j = 32-pin plastic j-leaded chip carrier (32j) speed option boot block location t = top boot block b = bottom boot block pmc device number r e b m u n t r a p t c c a ) s n ( t o o b n o i t a c o l e g a k c a p e r u t a r e p m e t e g n a r c j 5 5 - t 2 0 0 f 9 2 m p 5 5 p o t j 2 3 l a i c r e m m o c ) c 0 7 + o t c 0 ( c p 5 5 - t 2 0 0 f 9 2 m p p 2 3 c j 5 5 - b 2 0 0 f 9 2 m p m o t t o b j 2 3 c p 5 5 - b 2 0 0 f 9 2 m p p 2 3 c j 0 7 - t 2 0 0 f 9 2 m p 0 7 p o t j 2 3 l a i c r e m m o c ) c 0 7 + o t c 0 ( c p 0 7 - t 2 0 0 f 9 2 m p p 2 3 c j 0 7 - b 2 0 0 f 9 2 m p m o t t o b j 2 3 c p 0 7 - b 2 0 0 f 9 2 m p p 2 3 c j 0 9 - t 2 0 0 f 9 2 m p 0 9 p o t j 2 3 l a i c r e m m o c ) c 0 7 + o t c 0 ( c p 0 9 - t 2 0 0 f 9 2 m p p 2 3 c j 0 9 - b 2 0 0 f 9 2 m p m o t t o b j 2 3 c p 0 9 - b 2 0 0 f 9 2 m p p 2 3 note: valid combination list for the pm29f002. please consult the local pmc sales office, sales representa- tives or distributors to confirm the availability of specific valid combination and delivery schedule.
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 pin descriptions 4 l o b m y se p y tn o i t p i r c s e d 7 1 a - 0 at u p n i . r e t s i g e r d n a m m o c d n a s e s s e r d d a y r o m e m r o f : s t u p n i s s e r d d a . e l c y c e t i r w a g n i r u d d e h c t a l y l l a n r e t n i e r a s e s s e r d d a # e ct u p n i s e i r t i u c r i c l a n r e t n i s ' e c i v e d e h t s e t a v i t c a w o l # e c : e l b a n e p i h c d n a e c i v e d e h t s t c e l e s e d h g i h # e c . n o i t a r e p o e c i v e d r o f . n o i t p m u s n o c r e w o p e h t e c u d e r o t e d o m y b d n a t s o t n i s e h c t i w s . e l b a t s c i t s i r e t c a r a h c c d o t r e f e r e s a e l p # e wt u p n i s i # e w . n o i t a r e p o e t i r w r o f e c i v e d e h t e t a v i t c a : e l b a n e e t i r w . w o l e v i t c a # e ot u p n i d a e r a g n i r u d s r e f f u b a t a d s ' e c i v e d e h t l o r t n o c : e l b a n e t u p t u o . w o l e v i t c a s i # e o . e l c y c 7 o / i - 0 o / i / t u p n i t u p t u o , n o i t a r e p o m a r g o r p g n i r u d a t a d y a r r a s t u p n i : s t u p t u o / s t u p n i a t a d g n i r u d d e h c t a l y l l a n r e t n i s i a t a d . e v i t c a e r a # e w d n a # e c n e h w , e v i t c a e r a # e o d n a # e c n e h w . s e l c y c m a r g o r p d n a e t i r w e h t . e d o c e c i v e d r o e d o c r e r u t c a f u n a m , a t a d y a r r a s d n e s t u p t u o e h t e h t r o d e t c e l e s e d s i p i h c e h t n e h w e t a t s - i r t o t t a o l f s n i p a t a d e h t . d e l b a s i d e r a s t u p t u o v c c y l p p u s r e w o p e c i v e d d n gd n u o r g c nn o i t c e n n o c o n
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 block diagram device operation read operation the access of pm29f002 is similar as that of eprom. to obtain data at the outputs, three control functions must be satisfied: ce# is the chip enable and should be pulled low ( v il ). oe# is the output enable and should be pulled low ( v il ). we# is the write enable and should remains high ( v ih ) . boot block lockout the device has a software lockout feature to pre- vent the data in the boot block from being erased or reprogrammed. the boot block can be located at the top or bottom of the address location. the block size is 16 kbytes. once the lockout feature is enable, the boot block can not be erased or reprogrammed. data in the main memory block can still be updated through the regular programming method. the boot block lockout feature can be turned on by issuing a six-bus-cycle com- mand sequence. please refer to table 4 and chart 4. boot block lockout detection the state of the boot block lockout can be de- tected by software product identification entry. after entry, selects boot block address with a0 = ? 0 ? and a1 = ? 1 ? and then read i/o0. a data of ? 0 ? means the lock- out feature is disabled and the boot block can be erased or programmed. a data of ? 1 ? means the lockout fea- ture is enabled and the boot block is protected. prod- uct identification exit must be executed before the de- vice returns to read mode. product identification the product identification mode can be used to identify the device and the manufacturer by hardware or soft- ware operation. the hardware operation mode is acti- vated by applying a 12.0 volt on a9 pin, typically used by an external programmer to select the right program- ming algorithm for the device. for detail, please see bus operation modes in table 3. the software opera- tion mode is activated by three-bus-cycle command. please see software command definition in table 4. 5 we# ce# oe# command register ce,oe logic a0-a17 erase/program voltage generator high voltage switch i/o0-i/o7 i/o buffers data latch sense amp y-gating memory array address latch y-decoder x-decoder
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 device operation (continued) block erase the memory array is organized into five blocks: one 16 kbytes boot block, two 8 kbytes parameter blocks, one 96 kbytes and one 128 kbytes main blocks. a block erase operation allows to erase any individual block. pre-programs the block is not required prior to block erase operation. if the boot block lockout feature is enable, the block erase command attempts to erase the boot block will be ignored. the block erase com- mand is similar to chip erase command except for the last bus cycle command where the block addresses are used to select the block for erasure and the input data to the i/os is 30h. each block erase operation erases one block. block erase and chip erase are both internally controlled and timed. byte programming the programming is a four-bus-cycle operation and the data is programmed into the device (to a logical ? 0 ? ) on a byte-by-byte basis. please see software com- mand definition in table 4. a program operation is ac- tivated by writing the three-byte command sequence followed by one byte of data into the device. the ad- dress are latched on the falling edge of we# or ce# whichever occurs later, and the data is latched on the rising edge of we# or ce#, whichever occurs first. the internal control logic automatically handles the internal programming voltages and timing. a data ? 0 ? can not be programmed back to a ? 1 ? . only erase operation can convert ? 0 ? s to ? 1 ? s. the data# polling of i/o7 or toggle bit of i/o6 can be used to de- tect when the programming operation is completed. chip erase the entire memory array can be erased through a chip erase operation. pre-programs the device is not required prior to chip erase operation. chip erase starts after a six-bus-cycle chip erase command sequence. all commands will be ignored once the chip erase operation has started. the device will return back to read mode after the completion of chip erase. when the boot block lockout feature is enabled, the boot block will not be erased during a chip erase operation. only the parameter blocks and the main blocks will be erased. i/o7 data# polling the pm29f002 provides data# polling feature to indicate the process or the completion of a program or erase cycle. during a program cycle, an attempt to read the device will result in the complement of the last loaded data on i/o7. once the program cycle is completed, the true data of the last loaded data is valid on all out- puts. during a block or chip erase operation, an attempt to read the device will result a ? 0 ? on i/o7. after the erase cycle is completed, an attempt to read the device will result a ? 1 ? on i/o7. i/o6 toggle bit the pm29f002 also provides toggle bit feature as a method to detect the process or the end of a pro- gram or erase cycle. during a program or erase opera- tion, an attempt to read data from the device will result in i/o6 toggling between ? 1 ? and ? 0 ? . when the program or erase operation is complete, i/o6 will stop toggling and valid data will be read. toggle bit may be accessed at any time during a program or erase cycle. hardware data protection hardware data protection protects the device from unintentional erase or program operation. it is performed in the following ways: (a) v cc sense: if v cc is below 3.8 v (typical), the program function is inhibited. (b) write inhibit: holding any of the signal oe# low, ce# high or we# high inhibits a write cycle. (c) noise filter: pulses of less than 20 ns (typical) on the we# or ce# inputs will not initiate a write cycle. 6
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 k c o l be z i s k c o l be g n a r s s e r d d a 2 k c o l b n i a ms e t y b k 8 2 1h f f f f 1 - h 0 0 0 0 0 1 k c o l b n i a ms e t y b k 6 9h f f f 7 3 - h 0 0 0 0 2 2 k c o l b r e t e m a r a ps e t y b k 8h f f f 9 3 - h 0 0 0 8 3 1 k c o l b r e t e m a r a ps e t y b k 8h f f f b 3 - h 0 0 0 a 3 k c o l b t o o bs e t y b k 6 1h f f f f 3 - h 0 0 0 c 3 k c o l be z i s k c o l be g n a r s s e r d d a k c o l b t o o bs e t y b k 6 1h f f f 3 0 - h 0 0 0 0 0 1 k c o l b r e t e m a r a ps e t y b k 8h f f f 5 0 - h 0 0 0 4 0 2 k c o l b r e t e m a r a ps e t y b k 8h f f f 7 0 - h 0 0 0 6 0 1 k c o l b n i a ms e t y b k 6 9h f f f f 1 - h 0 0 0 8 0 2 k c o l b n i a ms e t y b k 8 2 1h f f f f 3 - h 0 0 0 0 2 table 1. top boot block address table (pm29f002t) table 2. bottom boot block address table ( pm29f002b) 7 memory blocks and addresses operating modes notes: 1. x can be v il , v ih or addresses. 2. v h = 12.0 v 0.5 v. 3. manufacturer code: 9dh; device code: 1dh (top boot), 2dh (bottom boot) table 3. bus operation modes e d o m# e c# e o# e ws s e r d d ao / i d a e rv l i v l i v h i x ) 1 ( d t u o e t i r wv l i v h i v l i xd n i y b d n a t sv h i xx x z h g i h e l b a s i d t u p t u oxv h i xx z h g i h n o i t a c i f i t n e d i t c u d o r p e r a w d r a h v l i v l i v h i = 7 1 a - 2 av = 9 a , x h ) 2 ( , v = 1 a l i v = 0 a , l i e d o c r e r u t c a f u n a m ) 3 ( v = 9 a , x = 7 1 a - 2 a h ) 2 ( , v = 1 a l i v = 0 a , h i e d o c e c i v e d ) 3 (
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 command definition 8 table 4. software command definition d n a m m o c e c n e u q e s s u b e l c y c s u b t s 1 e l c y c a t a d r d d a s u b d n 2 e l c y c a t a d r d d a s u b d r 3 e l c y c a t a d r d d a s u b h t 4 e l c y c a t a d r d d a s u b h t 5 e c l y c a t a d r d d a s u b h t 6 e l c y c a t a d r d d a d a e r1d r d d a t u o e s a r e p i h c6h a a h 5 5 5h 5 5 h a a 2h 0 8 h 5 5 5h a a h 5 5 5h 5 5 h a a 2h 0 1 h 5 5 5 e s a r e k c o l b6h a a h 5 5 5h 5 5 h a a 2h 0 8 h 5 5 5h a a h 5 5 5h 5 5 h a a 2a b ) 1 ( h 0 3 e t y b m a r g o r p 4h a a h 5 5 5h 5 5 h a a 2h 0 a h 5 5 5d r d d a n i k c o l b t o o b t u o k c o l ) 3 , 2 ( 6h a a h 5 5 5h 5 5 h a a 2h 0 8 h 5 5 5h a a h 5 5 5h 5 5 h a a 2h 0 4 h 5 5 5 k c o l b t o o b t u o k c o l n o i t c e t e d ) 3 ( 3h a a h 5 5 5h 5 5 h a a 2h 0 9 h 5 5 5 a b ) 4 ( h 0 0 ) 5 ( a b ) 4 ( h 1 0 ) 5 ( t c u d o r p d i r e r u t c a f u n a m 3h a a h 5 5 5h 5 5 h a a 2h 0 9 h 5 5 5h d 9 h 0 0 x e c i v e d t c u d o r p ) t o o b p o t ( d i 3h a a h 5 5 5h 5 5 h a a 2h 0 9 h 5 5 5h d 1 h 1 0 x e c i v e d t c u d o r p ) t o o b m o t t o b ( d i 3h a a h 5 5 5h 5 5 h a a 2h 0 9 h 5 5 5h d 2 h 1 0 x d i t c u d o r p t i x e ) 6 ( 3h a a h 5 5 5h 5 5 h a a 2h 0 f h 5 5 5 d i t c u d o r p t i x e ) 6 ( 1h 0 f h x x x notes: 1. ba = block address of the block to be erased. 2. when the boot block lockout feature is enabled, the boot block will not be erased when a chip erase command or a block erase command for boot block erasure is issued. once the boot block is not protected, the boot block will be erased when a chip erase command or a block erase command for boot block erasure is issued. 3. after completion of the boot block lockout enable or detection command, the product id exit com- mand must be issued to return to standard read mode. 4. ba = block address of the boot block; for top boot block location, a0 = ? 0 ? , a1 = ? 1 ? , and a14-a17 = ? 1 ? where a2-a13 = don ? t care; for bottom boot block location, a0 = ? 0 ? , a1 = ? 1 ? , and a14-a17 = ? 0 ? where a2-a13 = don ? t care. 5. i/o0 = ? 1 ? means boot block lockout is enabled, i/o0 = ? 0 ? means boot block lockout is disabled. 6. either one of the product id exit command can be used.
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 device operations flowcharts automatic programming 9 chart 1. automatic programming flowchart start load data aah to address 555h load data 55h to address 2aah load data a0h to address 555h load program data to program address i/o7 = data? or i/o6 stop toggle? last address? programming completed no no yes yes address increment
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 automatic erase chart 2. automatic erase flowchart chip erase command block erase command device operations flowcharts (continued) start write chip or block erase command data = ffh? or i/o6 stop toggle? erasure completed yes no load data aah to address 555h load data 55h to address 2aah load data 80h to address 555h load data aah to address 555h load data 55h to address 2aah load data 10h to address 555h (3) load data aah to address 555h load data 55h to address 2aah load data 80h to address 555h load data aah to address 555h load data 55h to address 2aah load data 30h to block address (1,2,3) 10 notes: 1. please see software command definition in table 1 and table 2 for block addresses. 2. only erase one block per each block erase cycle. 3. when the boot block lockout feature has been enabled, the boot block will not be erased.
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 software product identification exit load data aah to address 555h load data 55h to address 2aah load data 90h to address 555h enter product identification mode (1,2) load data aah to address 555h load data 55h to address 2aah load data f0h to address 555h exit product identification mode (3) load data f0h to address xxxh exit product identification mode (3) or 11 chart 3. software product identification entry/exit flowchart software product identification entry device operations flowcharts (continued) notes: 1. manufacturer code is read when a0-a17 = xx00h, where x = don ? t care; device code is read when a0-a17 = xx01h. 2. manufacturer code = 9dh; device code = 1dh (top boot device); device code = 2dh (bottom boot device). 3. the device returns to standard read operation.
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 boot block lockout enable (1,2) load data aah to address 555h load data 55h to address 2aah load data 80h to address 555h load data aah to address 555h load data 55h to address 2aah load data 40h to address 555h pause 500 ms boot block lockout enabled notes: 1. please call manufacturer for the command code to disable the boot block lockout. 2. after excuting the boot block lockout command, the product id exit command must be issued to return to standard read mode. 12 chart 4. boot block lockout enable flowchart device operations flowcharts (continued)
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 s a i b r e d n u e r u t a r e p m e t 5 6 - o 5 2 1 + o t c o c e r u t a r e p m e t e g a r o t s 5 6 - o 5 2 1 + o t c o c n i p 9 a t p e c x e s n i p l l a n o d n u o r g o t t c e p s e r h t i w e g a t l o v t u p n i ) 2 ( v 5 2 . 6 + o t v 5 . 0 - n i p 9 a n o d n u o r g o t t c e p s e r h t i w e g a t l o v t u p n i ) 3 ( v 0 . 3 1 + o t v 5 . 0 - d n u o r g o t t c e p s e r h t i w e g a t l o v t u p t u o l l a v o t v 5 . 0 - c c v 6 . 0 + v c c ) 2 ( v 5 2 . 6 + o t v 5 . 0 - dc and ac operating range r e b m u n t r a p 2 0 0 f 9 2 m p e r u t a r e p m e t g n i t a r e p o 0 o 0 7 o t c o c y l p p u s r e w o p c c v v 5 . 5 - v 5 . 4 13 absolute maximum ratings (1) notes: 1. stresses under those listed in ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. the functional operation of the device or any other conditions under those indicated in the operational sections of this specifica- tion is not implied. exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. maximum dc voltage on input or i/o pins are +6.25 v. during voltage transitioning period, input or i/o pins may overshoot to v cc + 2.0 v for a period of time up to 20 ns. minimum dc voltage on input or i/o pins are -0.5 v. during voltage transitioning period, input or i/o pins may undershoot gnd to -2.0 v for a period of time up to 20 ns. 3. maximum dc voltage on a9 pin is +13.0 v. during voltage transitioning period, a9 pin may overshoot to +14.0 v for a period of time up to 20 ns. minimum dc voltage on a9 pin is -0.5 v. during voltage transitioning period, a9 pin may undershoot gnd to -2.0 v for a period of time up to 20 ns.
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 dc characteristics l o b m y sr e t e m a r a pn o i t i d n o cn i mp y tx a ms t i n u i i l t n e r r u c d a o l t u p n iv n i v o t v 0 = c c v , c c v = x a m c c 1 a i o l t n e r r u c e g a k a e l t u p t u ov o / i v o t v 0 = c c v , c c v = x a m c c 1 a i 1 b s v c c s o m c t n e r r u c y b d n a t sv = # e o , # e c c c v 5 . 0 1 . 05a i 2 b s v c c l t t t n e r r u c y b d n a t sv = # e c h i v o t c c 2 . 03a m i 1 c c v c c t n e r r u c d a e r e v i t c ai ; z h m 5 = f t u o a m 0 =0 10 3a m i 2 c c ) 1 ( v c c t n e r r u c e s a r e / m a r g o r p0 40 6a m v l i e g a t l o v w o l t u p n i5 . 0 -8 . 0v v h i e g a t l o v h g i h t u p n i0 . 2v c c 5 . 0 +v v l o e g a t l o v w o l t u p t u oi l o v , a m 8 . 5 = c c v = n i m c c 5 4 . 0v v h o e g a t l o v h g i h t u p t u oi h o 0 0 4 - = v , a c c v = n i m c c 4 . 2v 14 read operations characteristics ac characteristics - b m y s l o r e t e m a r a p 5 5 - 2 0 0 f 9 2 m p0 7 - 2 0 0 f 9 2 m p0 9 - 2 0 0 f 9 2 m p s t i n u n i mx a mn i mx a mn i mx a m t c r e m i t e l c y c d a e r5 50 70 9s n t c c a y a l e d t u p t u o o t s s e r d d a5 50 70 9s n t e c y a l e d t u p t u o o t # e c5 50 70 9s n t e o y a l e d t u p t u o o t # e o0 35 30 4s n t f d z h g i h t u p t u o o t # e o r o # e c00 205 200 3s n t h o r o # e c , # e o m o r f d l o h t u p t u o t s r i f d e r u c c o r e v e h c i h w , s s e r d d a 000s n t s c v v c c e m i t p u - t e s0 50 50 5s note: 1. characterized but not 100% tested.
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 read operations ac waveforms output test load input test waveforms and measurement level 15 ac characteristics (continued) pin capacitance ( f = 1 mhz, t = 25 c ) p y tx a ms t i n us n o i t i d n o c c n i 46 f pv n i v 0 = c t u o 82 1f pv t u o v 0 = note: these parameters are characterized and are not 100% tested. address valid t rc t acc t ce t oe t df t oh output valid high z address ce# oe# we# output v cc t vcs 5.0 v 1.8 k 1.3 k output pin 100 pf 3.0 v 0.0 v 1.5 v ac measurement level input
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 16 write (program/erase) operations characteristics l o b m y sr e t e m a r a p 5 5 - 2 0 0 f 9 2 m p0 7 - 2 0 0 f 9 2 m p0 9 - 2 0 0 f 9 2 m p s t i n u n i mx a mn i mx a mn i mx a m t c w e m i t e l c y c e t i r w5 50 70 9s n t s a e m i t p u - t e s s s e r d d a 000 s n t h a e m i t d l o h s s e r d d a5 45 40 5s n t s c e m i t p u - t e s # e c 000 s n t h c e m i t d l o h # e c 000 s n t s w e m i t p u - t e s # e w 000 s n t h w e m i t d l o h # e w 000 s n t s d e m i t p u - t e s a t a d0 30 35 4s n t h d e m i t d l o h a t a d 000 s n t p w h t d i w e s l u p e t i r w5 35 35 4s n t h p w h g i h h t d i w e s l u p e t i r w0 20 20 2s n t p b e m i t g n i m m a r g o r p e t y b0 50 50 5s t c e e m i t e l c y c e s a r e k c o l b r o p i h c0 0 10 0 10 0 1s m t s c v v c c e m i t p u - t e s0 50 50 5s ac characteristics (continued) program operations ac waveforms - we# controlled t ch t cs t wp t wph t bp t dh t ds t ah t as 555 555 address 2aa aa 55 a0 input data valid data data in a0 - a17 oe# we# ce# program cycle t wc v cc t vcs
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 17 ac characteristics (continued) chip erase operations ac waveforms t wh t ws t wp t wph t bp t dh t ds t ah t as 555 555 address 2aa aa 55 a0 input data valid data data in a0 - a17 oe# ce# we# program cycle t wc v cc t vcs program operations ac waveforms - ce# controlled aa 55 55 10 80 aa 555 2aa 555 555 2aa t ec t wph t wp t as t ah t dh t ds ao - a17 we# ce# oe# data in t wc 555 v cc t vcs
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 block erase operations ac waveforms aa 55 55 30 80 aa 555 2aa 555 555 2aa block address t ec t wph t wp t as t ah t dh t ds ao - a17 we# ce# oe# data in t wc v cc t vcs program/erase performance r e t e m a r a pt i n un i mp y tx a ms k r a m e r e m i t e s a r e k c o l bs m0 40 0 1 d n a m m o c e s a r e g n i t i r w m o r f n o i t e l p m o c e s a r e o t e m i t e s a r e p i h cs m0 40 0 1 d n a m m o c e s a r e g n i t i r w m o r f n o i t e l p m o c e s a r e o t e m i t g n i m m a r g o r p e t y b s 5 10 5 e l c y c - r u o f f o e m i t e h t s e d u l c x e n o i t u c e x e d n a m m o c m a r g o r p e c n a r u d n e e s a r e / m a r g o r ps e l c y c0 0 0 , 0 10 0 0 , 0 5 18 ac characteristics (continued) note: these parameters are characterized and are not 100% tested.
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 toggle bit ac waveforms 19 ac characteristics (continued) note: toggling either ce#, oe# or both oe# and ce# will operate toggle bit. data# polling ac waveforms t oeh we# ce# oe# i/o6 toggle stop toggling valid data t oe toggle data t df t oh t ch t ce t oeh t oe t df t oh valid data i/o7# we# ce# oe# i/o7 note: toggling either ce#, oe# or both oe# and ce# will operate data# polling.
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 32p 32-pin plastic dip dimensions in inches (millimeters) 32j 32-pin plastic leaded chip carrier dimensions in inches (millimeters) 20 package type information seating plane .120(3.05) .160(4.07) .090(2.29) .110(2.79) .014(.36) .022(.56) .015(.38) min .146(3.71) .162(4.11) top view side view .600(15.24) .625(15.88) .008(0.20) .013(0.33) 0 10 .625(15.88) .665(16.89) 1.640(41.7) 1.680(42.7) 17 32 16 pin 1 i.d. .537(13.64) .557(14.05) .040(1.02) .065(1.65) .005(.127) min pin 1 i.d. .585(14.86) .595(15.11) .547(13.89) .553(14.05) .050 ref. .026(.66) .032(.81) .447(11.35) .453(11.51) .485(12.32) .495(12.51) 025(.635)x30 .400 ref. .510(12.95) .530(13.46) .013(.33) .021(.53) .009 .015 .076(1.93) .095(2.41) .123(3.12) .140(3.56) seating plane
programmable microelectronics corp. issue date: march, 2001 rev: 1.0 pmc pm29f002 21 revision history e t a d. o n n o i s i v e rs e g n a h c f o n o i t p i r c s e d. o n e g a p 1 0 0 2 , h c r a m0 . 1n o i t a c i l b u p w e nl l a

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